RFRST=0, DRES=0, TFRST=0, FM=0
FIFO Control Register
| FM | FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 0 (0): Non-FIFO mode 1 (1): FIFO mode |
| RFRST | Receive FIFO Data Register Reset(Valid only in FCR.FM=1) 0 (0): Not reset to FRDRHL 1 (1): Reset to FRDRHL |
| TFRST | Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) 0 (0): Not reset to FTDRHL 1 (1): Reset to FTDRHL |
| DRES | Receive data ready error select bit(When detecting a reception data ready, the interrupt request is selected.) 0 (0): Reception data full interrupt (RXIn) 1 (1): Receive error interrupt (ERIn) |
| TTRG | Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) |
| RTRG | Receive FIFO data trigger number |
| RSTRG | RTS# Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) |